PowerDRC/LVS Overview
November 2014
Corporate background
2
Fastest & most accurate DRC technology
Founded in 2009. Privately held by KM Core
World-wide pr...
PowerDRC/LVS capabilities
3
DRC - design rules checking in layout
LVS – layout vs. schematic verification
NVN – schema...
4
Patent-pending One-Shot™ processing
One-shot Processing
Unique, encapsulation of rules,
layers & operations
Window ...
PowerDRC™
5
The main idea of PowerDRC/LVS is to speed up the process of physical verification
by using One-Shot™ proces...
Parallel processing
6
PowerDRC benefits from parallel processing of:
independent groups of rules
independent parts of ...
PowerDRC™- Performance on 1-32x CPUs
7
PowerDRC™- Performance on 1-32x CPUs (cont.)
8
FAB1, tech 180nm, 36x SRAM memory blocks ~ 20 sq.mm
1600
412
140
220 ...
Performance of XOR operation in multi-CPU mode
FAB2, tech 250nm, 32x DRAM memory blocks ~ 800 sq.mm total
2173
790
380...
Performance gain with hierarchical mode
10
As obtained on real world designs
4.5X
Faster
1.94X
Faster
1.84X
Faster...
PowerLVS™
11
Supports 7 effective comparison algorithms applied automatically and dynamically
depending on the type of ...
PowerLVS performance
Process node: 40nmLP; Hard IP: analog, logic gates and memory cells, ~ 380 million physical gates
E...
Unique features
Advantages from using efficient FLAT engine natively
Efficient usage of hardware resources (RAM and CPU)...
Run and Debug Environment (PowerRDE™)
14
Allows user to:
Adjust DRC and LVS run parameters
Save them in a run configur...
Proprietary and Confidential
15
Short Finder utility (graphical LVS debug component)
Proprietary and Confidential
 Su...
PowerDRC/LVS integration
16
PowerDRC/LVS has interoperability with:
Cadence Virtuoso – CDBA and OpenAccess
SpringSoft ...
Synergic Partnership (AWR)
AWR Corporation has been POLYTEDA OEM partner since 2009.
PowerDRC/LVS was integrated with An...
Supported technology nodes
18
Sign-off
UMC IHP Silanna MOSIS SCMOS
40nm: G & LP
65nm: LL, LP & SP
180nm: G & LL
250...
To get hand-on experience
Order trial version of PowerDRC/LVS online at:
www.polyteda.com/contact-us/submitrequest
• Tr...
Licensing details
• PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS
• PowerRDE GUI cockpit requires...
Support policy
• POLYTEDA is ready to provide offline (email) technical support based on
additional Support and Maintena...
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PowerDRC/LVS 2.0.1 released by POLYTEDA

POLYTEDA LLC a provider of semiconductor design software and PV-services, announced the general availability of PowerDRC/LVS version 2.0.1. This release is dedicated to delivering further significant improvements for multi-CPU mode and some new LVS functionality. From now XOR operation supports multi-CPU mode to dramatically increase performance
Published on: Mar 4, 2016
Published in: Small Business & Entrepreneurship      
Source: www.slideshare.net


Transcripts - PowerDRC/LVS 2.0.1 released by POLYTEDA

  • 1. PowerDRC/LVS Overview November 2014
  • 2. Corporate background 2 Fastest & most accurate DRC technology Founded in 2009. Privately held by KM Core World-wide presence:  Headquarters and R&D and support team – Kiev, Ukraine Sales & Marketing provided by TEKSTART LLC ( US, Taiwan, Israel, Japan)
  • 3. PowerDRC/LVS capabilities 3 DRC - design rules checking in layout LVS – layout vs. schematic verification NVN – schematic netlists comparison XOR – diffing of layout versions Support of antenna rules, pads, latches and other special rules Fill layers generation Graphical diagnostics with visualization of violations and shorted nets
  • 4. 4 Patent-pending One-Shot™ processing One-shot Processing Unique, encapsulation of rules, layers & operations Window Scanning Unleash Using Core technology
  • 5. PowerDRC™ 5 The main idea of PowerDRC/LVS is to speed up the process of physical verification by using One-Shot™ processing that delivers maximum CPU efficiency per one rule check Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm Fastest and most accurate flat DRC engine on the market Predictable performance and behavior Multi-CPU operations for linear performance gain
  • 6. Parallel processing 6 PowerDRC benefits from parallel processing of: independent groups of rules independent parts of layout Parallel tasks may be run in multi-CPU mode on: a single host multi host grids like Platform LSF or SGE NEFELUS cloud service Scalability proven on 2, 4, 6, 8, 12, 16, 24, 32 CPUs
  • 7. PowerDRC™- Performance on 1-32x CPUs 7
  • 8. PowerDRC™- Performance on 1-32x CPUs (cont.) 8 FAB1, tech 180nm, 36x SRAM memory blocks ~ 20 sq.mm 1600 412 140 220 93 0 250 500 750 1000 1250 1500 1750 PowerDRC 2.0 @32x CPU cores PowerDRC 2.0 @16x CPU cores PowerDRC 2.0 @8x CPU cores PowerDRC 2.0 @4xCPU cores PowerDRC 2.0 @1xCPU core NEFELUS Cloud platform, CPU Intel Xeon E5-2680 V2 2.8 GHz - run tim e, seconds. Less is better
  • 9. Performance of XOR operation in multi-CPU mode FAB2, tech 250nm, 32x DRAM memory blocks ~ 800 sq.mm total 2173 790 380 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 PowerDRC 2.0 @8x CPU cores PowerDRC 2.0 @4xCPU cores PowerDRC 2.0 @1xCPU core AMD Opteron 8x CPU cores 2.6 GHz - run time, seconds. Less is better 9
  • 10. Performance gain with hierarchical mode 10 As obtained on real world designs 4.5X Faster 1.94X Faster 1.84X Faster Design Content: “A”: 75% logic & 25% memory “B”: 25% logic & 75% memory “C”: 2% logic & 98% memory
  • 11. PowerLVS™ 11 Supports 7 effective comparison algorithms applied automatically and dynamically depending on the type of encountered blocks to ensure accuracy at the highest level of performance Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm Predictable performance and behavior Supports extraction of array instances to get up to 10x performance increase Provides Multi-label, Floating-label, Hier cells and Open nets reports Graphical debug is provided by PowerRDE and Short Finder utility
  • 12. PowerLVS performance Process node: 40nmLP; Hard IP: analog, logic gates and memory cells, ~ 380 million physical gates Extraction of all devices: 11 hrs + 5 more hrs for output Comparison: 12.5 hrs Total LVS time: 28.5 hrs using 1 CPU core and 128 GB of RAM Process node: PL; Hard IP: LCD 1280x960: analog IP and pixel cell array, ~ 50 million physical gates Extraction of all devices: 2 min Comparison: 1 hr and 50 min Total LVS time: 1 hr and 52 min using 1 CPU and 8 GB of RAM 12
  • 13. Unique features Advantages from using efficient FLAT engine natively Efficient usage of hardware resources (RAM and CPU) Predictable performance 13
  • 14. Run and Debug Environment (PowerRDE™) 14 Allows user to: Adjust DRC and LVS run parameters Save them in a run configuration file Read a saved configuration Run PowerDRC/LVS View run progress Review results Debug violations, etc.
  • 15. Proprietary and Confidential 15 Short Finder utility (graphical LVS debug component) Proprietary and Confidential  Suggests a short location  Shorted net polygons in a table format  Allows to assign label for selected polygon  Allows to mark a polygon as ‘deleted’  Recalculates the shortest path  Interactive work in KLayout editor
  • 16. PowerDRC/LVS integration 16 PowerDRC/LVS has interoperability with: Cadence Virtuoso – CDBA and OpenAccess SpringSoft Laker – Native AWR Analog Office KLayout – Native Symica DE – demo mode
  • 17. Synergic Partnership (AWR) AWR Corporation has been POLYTEDA OEM partner since 2009. PowerDRC/LVS was integrated with Analog Office suite and is available for all Analog Office customers. More information and demo video are available at: www.polyteda.com/products-demo www.awrcorp.com/products/analog-office 17
  • 18. Supported technology nodes 18 Sign-off UMC IHP Silanna MOSIS SCMOS 40nm: G & LP 65nm: LL, LP & SP 180nm: G & LL 250nm 130nm 250nm 500-180nm
  • 19. To get hand-on experience Order trial version of PowerDRC/LVS online at: www.polyteda.com/contact-us/submitrequest • Try cloud version of PowerDRC/LVS as SaaS on NEFELUS Cloud - www.nefelus.com PowerDRC/LVS 2.0.1 – available officially from POLYTEDA since November 14, 2014 19
  • 20. Licensing details • PowerDRC/LVS is licensed on per-CPU basis separately for DRC and LVS • PowerRDE GUI cockpit requires its own license • Fill layer generation feature (PowerFIL) requires its own license • XOR operation feature (PowerXOR) requires its own license • Licensing employs FlexLM license manager • Licenses are bound either to hostID (MAC-address) or disk serial number or dongle flexID • Usual license duration is 1 year • Licenses are valid for all minor version updates but not for major ones, i.e. license for 1.7 is valid for 1.7.1 but not for 2.0 • Short-term licenses may be granted for trial purposes 20
  • 21. Support policy • POLYTEDA is ready to provide offline (email) technical support based on additional Support and Maintenance Agreement (available). • In urgent cases a hot fix version may be sent to the customer as soon as the issue is solved. 21

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