Process Integration Asad Mohammed Process Integration Intern – Photolithography Rich Berger - ATDF
Outline <ul><li>Process Integration </li></ul><ul><li>3 mask capacitor reticle </li></ul><ul><li>Layout </li></ul><ul><li...
Process Integration Layout Mask(Reticle) Preparation Recipe Wafer Fabrication Testing Specifications
3 mask Capacitor Reticle– 871AZ Dielectric constant  PolyGate SiO 2 Si Substrate Area A -Q E Separation d Area A +Q V
861  871 Changes oxide Floating gate Control gate N-Si Substrate <ul><li>Circle  Square </li></ul><ul><li>Backside c...
871AZ Layout and Fabrication Underlap Structures Overlap Structures MultiDot Structures Transistors CV structures Dummy Fi...
Test Wafers 7082901-7082904 7082902-02; Scratch probably due to wanding Close up without flash 7082904-01; Backside scratch
Electrical Testing Results
3D Reticle Multiple Wafer to Wafer Direct Copper Bonding Donor wafer aligned to substrate wafer
3D Die Layout <ul><li>Via Density Structures </li></ul><ul><li>Combs W and W/O Vias </li></ul><ul><li>Vias on metal </li><...
3D Reticle Fab
Other Reticles Worked on <ul><li>Multilevel Flash </li></ul><ul><li>– extra metal layer </li></ul><ul><li>E-Beam </li></...
Acknowledgements <ul><li>ACC </li></ul><ul><li>ATDF </li></ul><ul><li>Rich Berger </li></ul><ul><li>Romelia Distasio Kenne...
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Nano scholar february08_presentation

Presentation made at the end of the year long Nanoscholar program at Sematech Austin.
Published on: Mar 3, 2016
Published in: Business      Technology      
Source: www.slideshare.net


Transcripts - Nano scholar february08_presentation

  • 1. Process Integration Asad Mohammed Process Integration Intern – Photolithography Rich Berger - ATDF
  • 2. Outline <ul><li>Process Integration </li></ul><ul><li>3 mask capacitor reticle </li></ul><ul><li>Layout </li></ul><ul><li>Fabrication Cycle </li></ul><ul><li>E-Testing </li></ul><ul><li>3D Reticle </li></ul><ul><li>Typical Work Day </li></ul>
  • 3. Process Integration Layout Mask(Reticle) Preparation Recipe Wafer Fabrication Testing Specifications
  • 4. 3 mask Capacitor Reticle– 871AZ Dielectric constant  PolyGate SiO 2 Si Substrate Area A -Q E Separation d Area A +Q V
  • 5. 861  871 Changes oxide Floating gate Control gate N-Si Substrate <ul><li>Circle  Square </li></ul><ul><li>Backside contact  Top side contact </li></ul>More structures Dummy Fill Novel structures <ul><li>1E-7 ~ 5E-4 </li></ul>
  • 6. 871AZ Layout and Fabrication Underlap Structures Overlap Structures MultiDot Structures Transistors CV structures Dummy Fill Transistors CV structures FG Caps with sub FG Caps w/o sub Underlap Structures Overlap Structures MultiDot Structures Transistors CV structures Overlap Structures MultiDot Structures Transistors CV structures Large Caps UHFs Exposure Etch Deposition
  • 7. Test Wafers 7082901-7082904 7082902-02; Scratch probably due to wanding Close up without flash 7082904-01; Backside scratch
  • 8. Electrical Testing Results
  • 9. 3D Reticle Multiple Wafer to Wafer Direct Copper Bonding Donor wafer aligned to substrate wafer
  • 10. 3D Die Layout <ul><li>Via Density Structures </li></ul><ul><li>Combs W and W/O Vias </li></ul><ul><li>Vias on metal </li></ul><ul><li>All levels perfectly mirrored </li></ul><ul><li>Dummy fill </li></ul>
  • 11. 3D Reticle Fab
  • 12. Other Reticles Worked on <ul><li>Multilevel Flash </li></ul><ul><li>– extra metal layer </li></ul><ul><li>E-Beam </li></ul><ul><li> – Serps and Combs </li></ul>
  • 13. Acknowledgements <ul><li>ACC </li></ul><ul><li>ATDF </li></ul><ul><li>Rich Berger </li></ul><ul><li>Romelia Distasio Kenneth Matthews </li></ul><ul><li>Bruce Wilks </li></ul><ul><li>Gregory Smith </li></ul>

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