Bob Naber
Feb 27, 2005
2 22005 Tech Seminar
• Introduction
Bob Naber
• Back to the Future
Where is the value going?
Jim Hogan, General Partner, T...
3 32005 Tech Seminar
• Simulation Solutions
John Lewellen, Application Engineering,SIGMA-C
• Break 15
• Resist Calibration...
4 42005 Tech Seminar
!" # $
Accelerate
ramp
Maximize Yield
Enable DFM communication
Accelerate cycles of learning
Improve ...
5 52005 Tech Seminar
% $ &'(
• Accelerate process development
– Enable semiconductor manufacturers to maximize
the use of ...
of 5

naber agenda Sigma-C Synopsys Tech User forum

Published on: Mar 3, 2016
Source: www.slideshare.net


Transcripts - naber agenda Sigma-C Synopsys Tech User forum

  • 1. Bob Naber Feb 27, 2005
  • 2. 2 22005 Tech Seminar • Introduction Bob Naber • Back to the Future Where is the value going? Jim Hogan, General Partner, Telos Venture Partners • Mask topography/polarization effects for the 65nm and 45 nm nodes Peter Leunissen, IMEC • Applications of full chip CMP modeling Taber Smith PhD, President Praesagus • Wavefront-Based Tool Selection for Critical Level Imaging Jacek K. Tyminski PhD, Principal Engineer, Nikon Precision • When Simulation meets Reality : Signs and Coordinate Systems Bernd Geh, PhD, Carl Zeiss/ASML-Technology Development Center • Enabling nanoscale IC Yield Enhancement Bob Pack , HPL
  • 3. 3 32005 Tech Seminar • Simulation Solutions John Lewellen, Application Engineering,SIGMA-C • Break 15 • Resist Calibration Methodology Peter Brooker, Application Engineering, SIGMA-C • High-Throughput Hybrid Optical Maskless Lithography Mike Fritze PhD, MIT Lincoln Laboratories • Lithography Simulation at FhG IISB - new modeling approaches and future developments Andreas Erdmann PhD, Lithography Simulation Dept., Fraunhofer IISB • Determining ROI and Productivity Benefits of Lithographic Simulation David Jimenez, President, Wright Williams & Kelly, Inc. • Close / Reception Bob Naber
  • 4. 4 42005 Tech Seminar !" # $ Accelerate ramp Maximize Yield Enable DFM communication Accelerate cycles of learning Improve cycle time Accelerate Development The risk/reward of chip development 1 Changing demand and market competition have compressed product lifecycles, resulting in shorter duration revenue opportunities : Simulation reduces risks and improves reward 1 http://www.techonline.com/community/21478
  • 5. 5 52005 Tech Seminar % $ &'( • Accelerate process development – Enable semiconductor manufacturers to maximize the use of their current-generation exposure tools – Improve time to market by early definition and verification of your lithography strategy • Improve time to volume manufacturing – Enable reliable and consistent prediction of the output of the lithography process – Enable methodical tuning of the lithography process, design structures, and mask layout • Maximize productivity and yield – Allow the development of processes and products with significantly increased production yields by reducing the occurrence of faults – Increase the yield advantage further by closing the current gap between chip design and manufacturing using the customer’s DFM software tools - 0 .4 0 - 0 .3 0 - 0 .2 0 - 0 .1 0 0 .0 0 0 .1 0 0 .2 0 0 .3 0 0 .4 0 X [µ m ] - 0 .1 0 - 0 .0 5 0 .0 0 0 .0 5 0 .1 0 0 .1 5 0 .2 0 Z [µ m ] - 0 .4 0 - 0 .3 0 - 0 .2 0 - 0 .1 0 0 .0 0 0 .1 0 0 .2 0 0 .3 0 0 .4 0 X [µ m ] - 0 .1 0 - 0 .0 5 0 .0 0 0 .0 5 0 .1 0 0 .1 5 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .5 0 Z [µ m ]

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