Rev A 01/2015
FEATURES
 Designed to be implemented with minimal logic resources.
 Eight-bit bi-directional data bus.
 C...
Page 2 Copyright © Multilabs – 2015 All rights reserved
THIS PAGE LEFT BLANK INTENTIONALLY
Copyright © Multilabs – 2009 All rights reserved Page 3
SECTION 1
CONNECTIONS
 Pin Description
 Signal Description
Page 4 Copyright © Multilabs – 2015 All rights reserved
GND
76
51
26
1 ●
N
C
A
O
N
R
O
E PROCESSOR
2
3
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5
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7
8
9
10
11
1...
Copyright © Multilabs – 2009 All rights reserved Page 5
PIN NAME PIN NUMBER FUNCTION
A11 28 Address bus bit 11
A12 95 Addr...
Page 6 Copyright © Multilabs – 2015 All rights reserved
SIGNAL DESCRIPTION
Address Bus (A0 – A15)
The address line outputs...
Copyright © Multilabs – 2009 All rights reserved Page 7
SECTION 2
FUNCTIONAL DESCRIPTION
 Internal Registers
 Addressing...
Page 8 Copyright © Multilabs – 2015 All rights reserved
INTERNAL REGISTERS
Accumulator
The accumulator is a general purpos...
Copyright © Multilabs – 2009 All rights reserved Page 9
ADDRESSING MODES
Absolute Addressing
In absolute addressing the se...
Page 10 Copyright © Multilabs – 2015 All rights reserved
ADDRESS SPACE USAGE
With the exception of three address spaces th...
Copyright © Multilabs – 2009 All rights reserved Page 11
SUBROUTINES
Because the primary design goal of the processor was ...
Page 12 Copyright © Multilabs – 2015 All rights reserved
SECTION 3
INSTRUCTION SET
 Instruction Set
Copyright © Multilabs – 2009 All rights reserved Page 13
INSTRUCTION SET
ADD ADD Add Memory to Accumulator ADD
Operation: ...
Page 14 Copyright © Multilabs – 2015 All rights reserved
BZS BZS Branch on Zero Set BZS
Operation: (PC + 1) → PCL on Z = 1...
Copyright © Multilabs – 2009 All rights reserved Page 15
LDA LDA Load Accumulator from Memory LDP
Operation: M → A C Z
− ▲...
Page 16 Copyright © Multilabs – 2015 All rights reserved
ROR ROR Rotate Accumulator Right through Carry ROR
Operation: See...
Copyright © Multilabs – 2009 All rights reserved Page 17
SUB SUB Subtract Memory from Accumulator SUB
Operation: A - M → A...
Page 18 Copyright © Multilabs – 2015 All rights reserved
APPENDICES
Copyright © Multilabs – 2009 All rights reserved Page 19
APPENDIX A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings:
S...
Page 20 Copyright © Multilabs – 2015 All rights reserved
Voltage Out Vs. Current
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
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Nano Core

Published on: Mar 3, 2016
Source: www.slideshare.net


Transcripts - Nano Core

  • 1. Rev A 01/2015 FEATURES  Designed to be implemented with minimal logic resources.  Eight-bit bi-directional data bus.  Compact instruction set of only 32 instructions to learn.  Four addressing modes. Immediate, direct page, direct page indirect, and absolute.  Addressable memory range of up to 65K bytes.  External reset pin.  Clock frequency based on internal logic delays and memory access time. Reno, NV 89521 ● TEL: (775) 852-7430 ● FAX: (775) 852-7430 ● WEB: www.multilabs.net N C A O N R O E PROCESSOR N C A O N R O EPROCESSOR GENERAL DESCRIPTION The N C A O N R O E Processor is a CPU core that is designed to be implemented with minimal logic resources. The compact, yet effective, set of 32 instructions allows this core to be used as a central processor in small systems. This datasheet demonstrates the implementation in a Xilinx XC95144XL 144 macrocell CPLD in a 100-pin TQFP package. PIN CONFIGURATION 76 51 26 1 ● N C A O N R O E PROCESSOR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 7778798081828384858687888990919293949596979899100 R/W GND GND GND VCC A14 A13 A8 A9 GND GND GND GND GND GND GND GND GND RESET GND GND GND CLOCK GND GND VCC GND A11 GND GND GND GND GND GND A10 GND GND VCC GND GND GND GND D7 GND NC GND NC NC D6 GND VCC GND D5 GND GND GND VCC GND D4 GND D3 GND GND GND GND GND GND GND GND GND GND GND GND D2 GND GND D1 GND GND GND D0 A0 NC GND A1 A2 GND VCC GND A3 A4 A5 A6 A7 A12 A15 GND VCC GND GND
  • 2. Page 2 Copyright © Multilabs – 2015 All rights reserved THIS PAGE LEFT BLANK INTENTIONALLY
  • 3. Copyright © Multilabs – 2009 All rights reserved Page 3 SECTION 1 CONNECTIONS  Pin Description  Signal Description
  • 4. Page 4 Copyright © Multilabs – 2015 All rights reserved GND 76 51 26 1 ● N C A O N R O E PROCESSOR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 7778798081828384858687888990919293949596979899100 GND GND GND VCC A14 A13 A8 A9 GND GND GND GND GND GND GND GND RESET GND GND GND CLOCK GND GND VCC GND A11 GND GND GND GND GND GND A10 GND GND VCC GND GND GND GND D7 GND NC GND NC NC D6 GND VCC GND D5 GND GND GND VCC GND D4 GND D3 GND GND GND GND GND GND GND GND GND GND GND GND D2 GND GND D1 GND GND GND D0 A0 NC GND A1 A2 GND VCC GND A3 A4 A5 A6 A7 A12 A15 GND VCC GND GND R/W PIN DESCRIPTION Figure 1 This datasheet demonstrates the implementation in a Xilinx XC95144XL 144 macrocell CPLD in a 100- pin TQFP package. The following is a table of each pin’s description: PIN NAME PIN NUMBER FUNCTION A0 82 Address bus bit 0 A1 85 Address bus bit 1 A2 86 Address bus bit 2 A3 90 Address bus bit 3 A4 91 Address bus bit 4 A5 92 Address bus bit 5 A6 93 Address bus bit 6 A7 94 Address bus bit 7 A8 8 Address bus bit 8 A9 9 Address bus bit 9 A10 35 Address bus bit 10
  • 5. Copyright © Multilabs – 2009 All rights reserved Page 5 PIN NAME PIN NUMBER FUNCTION A11 28 Address bus bit 11 A12 95 Address bus bit 12 A13 7 Address bus bit 13 A14 6 Address bus bit 14 A15 96 Address bus bit 15 CLOCK 23 LVTTL Level system clock input (minimum ±100ppm and 45%/55% duty cycle or better) D0 81 Data bus bit 0 D1 77 Data bus bit 1 D2 74 Data bus bit 2 D3 61 Data bus bit 3 D4 59 Data bus bit 4 D5 53 Data bus bit 5 D6 49 Data bus bit 6 D7 43 Data bus bit 7 GND 2, 3, 4, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 24, 25, 27, 29, 30, 31, 32, 33, 34, 36, 37, 39, 40, 41, 42, 44, 46, 50, 52, 54, 55, 56, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 75, 76, 78, 79, 80, 84, 87, 89, 97, 99, 100 Power supply common NC 45, 47, 48, 83 No connection. R/W 1 Indicates direction of data transfers on data bus RESET 19 Resets processor back to power-up state VCC 5, 26, 38, 51, 57, 88, 98 +3.3V Power supply.
  • 6. Page 6 Copyright © Multilabs – 2015 All rights reserved SIGNAL DESCRIPTION Address Bus (A0 – A15) The address line outputs access data in memory, access data in I/O device registers, and/or effect logical operations in I/O or controller devices. Data Bus (D0 – D7) The data lines form an 8-bit bidirectional data bus which transfers data between the processor and memory or peripheral devices. Read/Write (R/W) This signal is generated by the processor to control the direction of data transfers on the data bus. This line is high except when the processor is writing to memory or a peripheral device. During a write this signal stays low for one clock cycle. There is no address or data hold time after the signal transitions back to high. Reset This input is used to reset or start the processor from a power down condition. During the time that this line is held low the processor is not running. System Clock (CLOCK) The processor requires a single clock from an external source which supplies a LVTTL level clock with a minimum ±100ppm and 45%/55% duty cycle or better. The frequency of the clock is based on the maximum speed of the internal logic and/or the access time of the memory and peripherals on the address bus. For example, when implemented in the Xilinx XC95144XL 10nS CPLD the maximum internal logic frequency is 21MHz. However, in this case, the speed would be limited by the external flash memory used on the test board. The maximum time for the address to reach the address pins is 4nS and the maximum time required for data to reach internal registers from the data pins is 9.3nS. Add this to an access time of 55nS for the flash memory and the total access time is 68.3nS. The system clock frequency can be no faster than 1/68.3nS, or 14.6MHz.
  • 7. Copyright © Multilabs – 2009 All rights reserved Page 7 SECTION 2 FUNCTIONAL DESCRIPTION  Internal Registers  Addressing Modes  Address Space Usage  Subroutines
  • 8. Page 8 Copyright © Multilabs – 2015 All rights reserved INTERNAL REGISTERS Accumulator The accumulator is a general purpose 8-bit register that stores the results of all arithmetic and logic operations from the ALU. In addition, the accumulator contains one of the two data bytes (except rotations which is a single data byte) used in these operations. The accumulator can be loaded with an immediate value, and also loaded from, and written to, external memory and peripherals. Direct Page The direct page is an 8-bit register that stores the most significant byte of the 16-bit address that is used during direct page addressing mode. During direct page addressing the value in the direct page register is concatenated with the value on the data bus to form a full 16-bit address. The direct page register can be loaded with an immediate value, and also loaded from external memory and peripherals. Instruction Register Instructions fetched from memory are latched into the 5-bit instruction register which is feed into the control unit and used to generate control signals for the various operations needed for the instruction. Program Counter The 16-bit program counter provides the addresses which step the processor through sequential instructions in a program. Each time the processor fetches an instruction from program memory the address is placed on the address bus. The counter is incremented each time an instruction or data is fetched from program memory. After power-up or a reset the program counter is loaded with 0. This is where program execution starts. Status The 2-bit processor status register contains the carry/borrow and zero flags. These flags are affected by various instructions, and can be used for conditional branching. The carry flag is inverted for borrow during subtraction operations. If borrow occurs during subtraction then the carry flag will be cleared. If borrow does not occur during subtraction then the carry flag will be set.
  • 9. Copyright © Multilabs – 2009 All rights reserved Page 9 ADDRESSING MODES Absolute Addressing In absolute addressing the second byte of the instruction specifies the least significant byte of the effective address while the third byte specifies the most significant byte. Thus, the absolute addressing mode allows direct access to the entire 64K of addressable memory. Direct Page Addressing In direct page addressing the second byte of the instruction specifies the least significant byte of the effective address while the value in the direct page register specifies the most significant byte. This addressing mode allows for shorter code and execution times by only needing to fetch a single byte from the instruction. Direct Page Indirect Addressing In direct page indirect addressing the second byte of the instruction specifies the least significant byte of the indirect address while the third byte specifies the most significant byte. The value stored at this address is then used to specify the least significant byte of the effective address while the value in the direct page register specifies the most significant byte. This mode works nearly the same as direct page addressing except that the least significant byte of the effective address is not part of the instruction but instead is retrieved indirectly from the absolute address specified in the instruction. This addressing mode is useful for indexing into a page of memory. The value at the absolute address can be incremented, decremented, or otherwise calculated by the processor as needed and then used as an index value into a page. Immediate Addressing In immediate addressing the operand is contained in the second byte of the instruction with no further memory addressing required. Implied Addressing In the implied addressing mode the address or register containing the operand is implicitly stated in the operation code of the instruction.
  • 10. Page 10 Copyright © Multilabs – 2015 All rights reserved ADDRESS SPACE USAGE With the exception of three address spaces the entire 64K of address space is open. The processor uses addresses 65533 through 65535 during a subroutine call. Since the processor does not have a stack these addresses are used to store information during the jump to, and the return from, the subroutine. These values can be used by the program to create a software stack if needed. This is explained in more detail in the Subroutines section later in this document. Since the program counter starts at zero, and these three addresses are used as temporary storage, a system designed around this processor needs to put program memory starting at the bottom of the address space and RAM memory starting at the top of address space. ADDRESS USAGE 65535 Least significant byte of the program counter. Saved by the subroutine instruction and read by the return from subroutine instruction. 65534 Most significant byte of the program counter. Saved by the subroutine instruction and read by the return from subroutine instruction. 65533 Value of accumulator when a subroutine is called. This value is not used by the return from subroutine instruction but can be reloaded into the accumulator by software prior to the return if required.
  • 11. Copyright © Multilabs – 2009 All rights reserved Page 11 SUBROUTINES Because the primary design goal of the processor was to work with limited logic resources a built-in stack pointer register, and supportive control circuitry, was not included in the design of this processor. As explained in the Address Space Usage section of this document the processor uses three bytes at the top of address space to store the program counter and the accumulator value when a subroutine is called. The return from subroutine instruction uses the addresses where the program counter was stored to re- load the program counter. The return from subroutine instruction does not re-load the accumulator since the program may be using the accumulator to return a value. But the value is provided just in case it is required and the program can re-load the accumulator. If a single subroutine is called nothing needs to be done by the program. But if subroutines are nested the program will need to maintain some method to store the program counter that the first subroutine instruction stored before a second subroutine is called. Since the processor uses the same addresses to store information each time a subroutine is called the values from the second subroutine call will overwrite the values from the first subroutine call. The program will also need to return the values to the specific locations in memory before returning from the first subroutine.
  • 12. Page 12 Copyright © Multilabs – 2015 All rights reserved SECTION 3 INSTRUCTION SET  Instruction Set
  • 13. Copyright © Multilabs – 2009 All rights reserved Page 13 INSTRUCTION SET ADD ADD Add Memory to Accumulator ADD Operation: A + M → A C Z ▲▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate ADD #Oper 10 2 5 Direct Page ADD Oper 00 2 6 AND AND Logically AND Memory with Accumulator AND Operation: A & M → A C Z − ▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate AND #Oper 12 2 5 Direct Page AND Oper 04 2 6 BCC BCC Branch on Carry Clear BCC Operation: (PC + 1) → PCL on C = 0 C Z (PC + 2) → PCH on C = 0 − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute BCC Oper 17 3 5 BCS BCS Branch on Carry Set BCS Operation: (PC + 1) → PCL on C = 1 C Z (PC + 2) → PCH on C = 1 − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute BCS Oper 18 3 5 BZC BZC Branch on Zero Clear BZC Operation: (PC + 1) → PCL on Z = 0 C Z (PC + 2) → PCH on Z = 0 − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute BZC Oper 1A 3 5
  • 14. Page 14 Copyright © Multilabs – 2015 All rights reserved BZS BZS Branch on Zero Set BZS Operation: (PC + 1) → PCL on Z = 1 C Z (PC + 2) → PCH on Z = 1 − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute BZS Oper 1B 3 5 CLC CLC Clear the Carry Flag CLC Operation: 0 → C C Z ▲ − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied CLC 0B 1 3 DDP DDP Decrement Direct Page Register DDP Operation: DP - 1 → DP C Z − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied DDP 09 1 3 IDP IDP Increment Direct Page Register IDP Operation: DP + 1 → DP C Z − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied IDP 0A 1 3 JMP JMP Jump to New Location JMP Operation: (PC + 1) → PCL C Z (PC + 2) → PCH − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute JMP Oper 16 3 5 JSR JSR Jump to New Location Saving Return Address (Subroutine) JSR Operation: (PC + 1) → PCL, (PC + 2) → PCH C Z (PC + 3) → M − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Absolute JSR Oper 1C 3 10
  • 15. Copyright © Multilabs – 2009 All rights reserved Page 15 LDA LDA Load Accumulator from Memory LDP Operation: M → A C Z − ▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate LDA #Oper 15 2 4 Direct Page LDA Oper 07 2 5 Direct Page Indirect LDA (Oper) 1E 3 7 Absolute LDA Oper 0E 3 6 LDP LDP Load Direct Page Register LDP Operation: M → DP C Z − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate LDP #Oper 19 2 4 Absolute LDP Oper 02 3 6 ORA ORA Logically OR Memory with Accumulator ORA Operation: A | M → A C Z − ▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate ORA #Oper 13 2 5 Direct Page ORA Oper 05 2 6 ROL ROL Rotate Accumulator Left through Carry ROL Operation: See description below C Z ▲ − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied ROL 03 1 4 Description: The contents of the accumulator are rotated one bit to the left through the carry flag. 7 6 5 4 3 2 1 0 C
  • 16. Page 16 Copyright © Multilabs – 2015 All rights reserved ROR ROR Rotate Accumulator Right through Carry ROR Operation: See description below C Z ▲ − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied ROR 0D 1 4 Description: The contents of the accumulator are rotated one bit to the right through the carry flag. RTS RTS Return from Subroutine RTS Operation: M → PC C Z − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied RTS 1D 1 5 SEC SEC Set the Carry Flag SEC Operation: 1 → C C Z ▲ − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Implied SEC 0C 1 3 STA STA Store Accumulator to Memory STA Operation: A → M C Z − − ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Direct Page STA Oper 08 2 4 Direct Page Indirect STA (Oper) 1F 3 6 Absolute STA Oper 0F 3 5 7 6 5 4 3 2 1 0C
  • 17. Copyright © Multilabs – 2009 All rights reserved Page 17 SUB SUB Subtract Memory from Accumulator SUB Operation: A - M → A C Z ▲▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate SUB #Oper 11 2 5 Direct Page SUB Oper 01 2 6 Flag assignments: M < A 1 → C, 0 → Z M = A 1 → C, 1 → Z M > A 0 → C, 0 → Z XOR XOR Logically XOR Memory with Accumulator XOR Operation: A ^ M → A C Z − ▲ ADDRESSING MODE ASSEMBLY LANGUAGE FORM OPCODE BYTES CYCLES Immediate XOR #Oper 14 2 5 Direct Page XOR Oper 06 2 6
  • 18. Page 18 Copyright © Multilabs – 2015 All rights reserved APPENDICES
  • 19. Copyright © Multilabs – 2009 All rights reserved Page 19 APPENDIX A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings: SYMBOL DESCRIPTION VALUE UNITS VCC Supply voltage relative to GND –0.5 to 4.0 V VIN Input voltage relative to GND –0.5 to 5.5 V VTS Voltage applied to 3-state output –0.5 to 5.5 V TSTG Storage temperature (ambient) –65 to +150 °C TJ Junction temperature +150 °C Recommended Operation Conditions: SYMBOL PARAMETER MIN MAX UNITS VCC Supply voltage for logic, input, and output buffers 3.0 3.6 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCC V DC Characteristic Over Recommended Operating Conditions: SYMBOL PARAMETER MIN MAX UNITS VOH Output high voltage (see Figure 19 for output voltage versus current) 2.4 VCC V VOL Output low voltage 0 0.4 V IIL Input leakage current - ±10 µA IIH I/O High-z leakage current (VIN= GND or VCC) - ±10 µA IIH I/O High-z leakage current (GND < VIN < VCC) - ±50 µA CIN I/O Capacitance - 10 pF ICC Operating supply current Typ 70 mA NOTE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions are not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
  • 20. Page 20 Copyright © Multilabs – 2015 All rights reserved Voltage Out Vs. Current 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 Voltage Current Figure 2

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