Published on: Mar 3, 2016
Transcripts - Narayana_Reddy_Lekkala_D_Resume
2816 Ellendale Pl, Los Angeles, CA, 90007 NARAYANA REDDY LEKKALA Phone: 310-866-6647 Email: firstname.lastname@example.org
OBJECTIVE: Actively seeking challenging Full-Time/Intern(OPT) position starting June 2016 in Design and Verification of VLSI Systems.
• University of Southern California, Los Angeles, CA, USA Aug 2014 - May 2016
Viterbi School of Engineering | Master of Science | Electrical Engineering
• Amrita School of Engineering, Coimbatore, Tamil Nadu, India July 2010 - June 2014
Bachelor of Technology | Electrical and Electronics Engineering
• Grader for EE 477L - MOS VLSI Circuit Design (Prof. Massoud Pedram) Aug – Dec 2015
Programming: UVM, System Verilog, Verilog, C/C++, Java, UNIX,PERL, Python, TCL, CTL
Tools: Cadence Virtuoso and SimVision, ModelSim, QuestaSim, NC Sim, Synopsys DC, Cadence Encounter, Synopsys PrimeTime, UPF
VLSI System Design, Verification of VLSI Systems, Computer Systems Architecture, Programming Systems Design
DDR3 Controller Design based on Denali’s model – RTL, DC, STA, P&R (Semi-Custom) Oct-Nov 2015
• RTL (Verilog) Design of Processing Logic, Cmd FIFO, Data FIFO, Return FIFO, Initialization engine, Ring buffer and SSTL.
• It supports Scalar, Burst and Atomic Read/Write Operations. Synthesized RTL using DC.
Design of 16-bit 5-stage Pipelined Processor using hardware and software components (Full-Custom) Jan-Apr 2015
• Schematic and Layout of CPU (Decoding logic, Register File, ALU, 512-bit SRAM memory) system supporting logical and arithmetic
instructions, bitwiseoperations. Perl was used front-end and back end.
• Area*Power*Delay product was reduced using dynamic logic, clock and data gating, power gating
32-bit MIPS Processor 5-stage Pipeline using RTL Style Coding – Verilog, Modelsim Nov 2014
• Implemented a 5 stage Pipelined Processor with early branch, late branch, Hazard Detection Unit, Forwarding Units using RTL Verilog.
• An in-order executing engine to manage data and control hazards. It supports R-type, Load, Store, Branch and Jump Instructions.
Parameterized FIFO Depth and Width Expansion using Perl Nov 2015
• Verilog design of FIFO with depth 8 and width 16. Perl script to take Verilog input parameters and generate Verilog code for expansion.
Implementation of UVM structure for UART and single clock FIFO – UVM, QuestaSim Jul 2015
• Constrained random based functional verification of a given UART and FIFO design using UVM (Universal Verification Methodology)
structure. UVM structure was written in System Verilog. The technology used was Questasim.
• The test bench components which include data packet, sequencer, driver, monitor, interface, scoreboard, active & passive agents
and environment were written using UVM base classes and macros.
• Designed intercommunication between components using TLM ports and included Assertion based verification in the test bench.
• Functionality of UART was verified under cases like verification of TX block and RX block separately; verification of both the blocks
working in parallel; Reset check; Identification of the start and end of a sequence in TX output.
• The functionality of FIFO was verified under four cases which include Empty to Full, Full to Empty, Full and Still Writing, Empty
and Still Reading.
Verification of two-clock FIFO and FSM using System Verilog Jun 2015
• A complete testbench in System Verilog to verify two-clock FIFO with separate classes for Driver (with interface) and Scoreboard.
• The driver class included functions to generate input, generate expected output, drive input and monitor output. The function to
generate input was made virtual to create a new Driver class that extended the original Driver class. In this new extended class,
data input had a constraint from 2^ (N - 1) to (2^ N) - 1. Here, N is the length of data input.
• Another part of the project was to implement a sequence detector (FSM) to verify properties like Reset-Check, One Hot-Check,
Sequence-Check and Miss-Check using Concurrent Assertions.
C++ Programming with Linked Lists Nov 2015
• Different kinds of linkedlist functions were implemented using C++. Some functions include rotateLeft, removeAdjacentEvens, reverseCopy.
• Functions were implemented without creating or destroying nodes and without changing values. Relinking the nodes was essential.
Functional Verification using System Verilog (Coverage-Driven Constrained-Random based) Jul 2015
• 4-bit adder and 3-bit multiplier were designed in System Verilog using an N-bit interface which included cover groups for all inputs.
• Testbench was written in System Verilog to verify the designs using Immediate Assertions and Constrained
Randomizations (for inputs) and to report score for each of the bins for Coverage.
Formal Verification using VIS (Verification Interacting with Synthesis) June 2015
• Equivalence between two RTL designs was verified using Logical Equivalence technique.Properties like liveness, fairness were written in
Computational Tree Logic (CTL).VIS tool was used to perform Model Checking and design was verified against these properties.
Statistical Timing Analysis Using Perl Script Jun 2015
• The aim of project was to implement the black box verification. Design was provided with inputs X1 and X2. The functionality of the design
was unknown. Inputs X1 and X2 in the testbench were generated through Verilog such that they followed Gaussian distribution.
• Developed a Perl script which computed the statistical analysis of the inputs X1 and X2 such as Mean, Variance, Auto-Covariance, Cross