Narendra Manchineella
E-mail:narendra414.m@gmail.com
Mobile: +91-9494888382 www.siliconsys.in
Institute of Silicon Systems...
Narendra Manchineella
E-mail:narendra414.m@gmail.com
Mobile: +91-9494888382 www.siliconsys.in
Institute of Silicon Systems...
Narendra Manchineella
E-mail:narendra414.m@gmail.com
Mobile: +91-9494888382 www.siliconsys.in
Institute of Silicon Systems...
of 3

Narendra Manchineella

Published on: Mar 3, 2016
Source: www.slideshare.net


Transcripts - Narendra Manchineella

  • 1. Narendra Manchineella E-mail:narendra414.m@gmail.com Mobile: +91-9494888382 www.siliconsys.in Institute of Silicon Systems Pvt. Ltd. Objective: To obtain a suitable challenging position in a professional organization further grow my talent, face responsibility and to create a team spirit within the working environment. Academic Credentials:  B.Tech in Electronics and Communication Engineering (ECE) from Kakinada Institute of Engineering & Technology (Affiliated to JNTU Kakinada) with an aggregate of 74.2% in 2015.  Diploma in Electronics and Communication Engineering (ECE) from A.A.N.M. & V.V.R.S.R. Polytechnic (State Board of Technical Education and Training) with an aggregate of 82.3% in 2012.  SSC (10th) from Ravindra Bharathi Public School (Board of Secondary Education) with an aggregate of 79.5% in 2009. Professional Training: Professional training on Custom Layout Designing from Institute of Silicon Systems Pvt. Ltd., Hyderabad from 4th May, 2015 to 31st July, 2015. Cadence Tools: Experience in Custom Layout Design.  Virtuoso Layout (L/XL) Editor - Floor Planning and Routing  Assura Verification -DRC and LVS  PVS Verification - DRC and LVS  Technology -TSMC 130nm and GPDK 45nm Custom Layout Projects: Tools: Virtuoso Layout Editor (L/XL), Assura and PVS. Digital Layout Designs: Project 1: Standard Cell Layout Designs Cells Designed: INVERTER, NAND, AND, NOR, OR, EX-OR, EX-NOR, MUX and D-Flip Flop. Targeted Technology: TSMC 130nm Role: Developing the Standard cells from Spice Net list and verify errors. Challenges: Creating devices manually, maintain equal Cell height for all cells in-terms of no. of metal track, carving, maintain Half DRC rules and De-bugging errors (DRC and LVS).
  • 2. Narendra Manchineella E-mail:narendra414.m@gmail.com Mobile: +91-9494888382 www.siliconsys.in Institute of Silicon Systems Pvt. Ltd. Analog Layout Designs: Targeted Technology: GPDK 45nm Role: Development of layout from schematic, providing critical matching for devices and verifying DRC and LVS for both top level and bottom level blocks. Project 2: Level Shifter Description: It is a compact device used for chip voltage level shifting. Challenges: Take care of PSUB2 (Deep N-well), eliminating noise coupling for high voltage devices, antenna effect, take care of signal flow and draw the layout in optimized way. Project 3: Operational Amplifier (Op-Amp) Description: It is a DC differential amplifier which produces high gain by providing proper feedback. Challenges: Critical matching for Diff-pair and current mirrors, signal flow, provide dummy's to protect the critical devices, provide guard rings, layout compactness and protect critical nets from noise coupling. Project 4: Band Gap Reference (BGR) Description: It is a device which provides a constant voltage irrespective of temperature variations and input violations. Challenges: Floor planning, power routing, taken care of EM and IR drop, device matching with respect to PVT, protecting critical nets (shielding) from noise coupling, signal flow and compact way. Project 5: Digital to Analog Converter (8-bits) Description: It scales digital reference signal as an analog output signal according to the digital input given (Switches to R-2R network). Challenges: Providing proper matching for resistor network(R-2R), match the critical nets to meet the same delay, device matching with respect to PVT, taken care of EM and IR drop, provided more care on latch-up issues, taken care of critical nets, antenna effect, provide proper bias from sources and signal flow. Project 6: Phase Locked Loop (PLL) Description: A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Challenges: Floor planning, power routing, taken care of EM, device matching with respect to PVT as well from (STI, LOD, WPE),protecting critical nets from less parasites(shielding), avoiding latch-up issues, capacitor matching, creating standard cells with respect to maintain cell height and optimizing way.
  • 3. Narendra Manchineella E-mail:narendra414.m@gmail.com Mobile: +91-9494888382 www.siliconsys.in Institute of Silicon Systems Pvt. Ltd. Skills Gained:  Analyze technology files, layers, rule files, device formation technology.  Knowledge on device matching, noise coupling, latch up effects, electro migration, antenna effect, back gate effect, ESD, WPE, STI, LOD.  Understanding signal flow to acquire an optimum floor plan and power plan.  Debugging DRC and LVS violations.  Protecting devices from less parasites Academic Project: Title: “Flat Wheel Detection” Role: Team Leader Description: The main object of the project is, by using the accelerometer, to detect the flat wheel of a train by using accelerometers while train is in motion (10KMPH - 150 KMPH).In this project accelerometer sensors are used to identify the flatness of the train wheel by analyzing the vibrations of sleepers. These vibrations are created whenever train passes on the railway track and the accelerometers which are placed on the sleeper will give corresponding analog voltages as their output by sensing those vibrations. After that these analog voltages are converted into digital signals and transmitted to remote place by using micro controller. A software tool is used to analyze those signals and to detect the presence of flat wheel and position of flat wheel if any flat wheel is present for a train. Such way the detection of flat wheel is done for a moving train. We can avoid the train accidents caused by derailment (which is occurred due to flat wheel) by replacing the flat wheel with a normal wheel. Internship:  Completed 1month (4weeks) project work based on DCS (Distributed Control System) and PLC (Programmable Logic Control) with a client of NFCL Kakinada.  Completed industrial training (6months) as per the curriculum of SBTET of Andhra Pradesh at Efftronics Systems Pvt. Ltd., Vijayawada. Personnel Details:  Father’s Name : Venkateswara Rao M  Mother’s Name : VenkataRamana M  Date of Birth : 25th August, 1993  Languages Known : English, Telugu  Current Location : Hyderabad (Flexible to migrate)

Related Documents