2418 South Espina Street Apt #12, Las Cruces, NM, 88001 575-650-7820
Project 1: Power Management Circuits for Wearable Devices (Power Management in IC)
(March 15-May 15, 2015)
 Team project ...
of 2

NarendraResume (1)

Published on: Mar 3, 2016

Transcripts - NarendraResume (1)

  • 1. NARENDRA NAIDU LINGUTLA 2418 South Espina Street Apt #12, Las Cruces, NM, 88001 575-650-7820 CAREER SUMMARY Masters student in Electrical Engineering with a minor in Management; assistant for professor in a research project that involved creating a 4ary FSK-OOK non-coherent wireless communication system. Strong background in coding, programming, computers, communications. Worked as a Graduate Assistant in the Nursing department as the head assistant. Learned managing a crew of people and a large amount of projects in a short amount of time. OPT begins February first. EDUCATION Master of Science, Major: Electrical Engineering Minor: Business Management G.P.A: 3.58 New Mexico State University, Las Cruces, NM Dec 2015 Bachelor of Technology, Major: Electronics Communication Engineering G.P. A: 3.79 Jawaharlal Nehru Technological University, India May 2012 SKILLS  Programming Languages: C, MATLAB, Verilog, system Verilog, VHDL, Python, Perl, TCL, LaTeX  Tools: Cadence Virtuoso, Cadence Encounter, Cadence Allegro, Cadence OrCAD/PSpice, Xilinx, Arduino KNOWLEGDE/COURSES  Digital Communication – Learned modulation techniques for transmitting digital data over commercial networks (FSK, PSK, ASK, OOK), implemented in MATLAB  Analog and digital VLSI – Did analysis, design, simulation, layout, and verification of CMOS, analog building blocks including references, OP-AMPS, switches, comparators, digital building blocks including static and dynamic logic design, memory circuits, arithmetic operators, and digital phase-locked loops on Cadence Virtuoso IBM 0.18nm technology  Power Management in IC – Designed and analysis of PMIC including linear voltage regulators, voltage references, buck, boost, buck-boost DC-DC converters, and charge pumps on Cadence Virtuoso IBM 0.18nm technology  ASIC design – Wrote RTL level code for ASIC, design and synthesis, logic and timing verification, and Verilog on Xilinx FPGA board  A/D and D/A Converter Design – Learned practical design of integrated data converters in CMOS/BJT technologies, OP- AMPS, comparators, sample and holds, MOS switches, element mismatches, Nyquist rate converter architectures: flash, successive approximation, charge redistribution, algorithmic, two step, folding, interpolating, pipelined, and delta-sigma converters  RF Microelectronics – Learned analysis, design and implementation of RF integrated circuits in CMOS/BJT technologies, low noise amplifiers and mixers, power amplifiers, wideband amplifiers, oscillators, and phase- locked frequency synthesizers. Written final report of LNA based on IEEE paper EXPERIENCE Research project #1: 4ary FSK-OOK non-coherent wireless communication system (Research Assistant; May 2014 – November 2015) Klipsch School of Electrical and Computer Engineering, New Mexico State University, New Mexico, USA  Designed communication system with low power, low complexity, and high data rate for ultra-wide band wireless communication system  Designed modulation (transmitter) and demodulation (receiver) with technique 4-ARY FSK-OOK, simulated the same model using MATLAB for performance and BER, giving me a fuller understanding and ability with coding languages in general Research project #2: 4ary FSK-OOK non-coherent wireless communication system (Research Assistant; May 2014- 2015)  Build PCB using Cadence Capture and Cadence Allegro/OrCAD and wrote HDL (Verilog) for Xilinx FPGA  Built current-starved ring oscillator and phase-locked-loop as frequency synthesizer for transmitter in Cadence Virtuoso  Used function generator and four channel oscilloscope for testing Verilog code dumped in FPGA  Made a step-by-step manual for Cadence Allegro on how to build a PCB design, to be used for professor in an undergraduate course  Self-initiated, of my own initiative to learn a new language, to implement phase locked loop in Verilog-AMS and Verilog-A in Cadence Virtuoso
  • 2. Project 1: Power Management Circuits for Wearable Devices (Power Management in IC) (March 15-May 15, 2015)  Team project with member of three dividing the blocks equally for completion  Learned to work in a team; independently and interdependently working on parts with people and alone when the situation called  Learned how to work and deliver results while under the stress of an impending deadline  IBM’s CMOS7RF 180nm technology is used to design LDO, reference voltage, linear voltage regulators, buck, boost, buck-boost DC-DC converters, and charge pumps  Designed buck converter, boost converter, and low drop out regulator; also implemented control loop for converters Project 2: Clock-Multiplying Digital Phase Locked Loop (Oct 14- Dec 14, 2014)  Goal of this project to generate output signal in multiplicity of input signal and output frequency is fed to the input signal for feedback  Team of three designed and simulation of phase detector, push pull charge pump, loop filter, VCO, clock buffer, and frequency divider in Cadence Virtuoso IBM CMOS7RF 180nm technology  Took charge of project by managing project and team; completed blocks by me are phase detector, frequency divider, and VCO  Presented project in front of class and described about importance and lesson learned throughout the project  Learned skills like verbal communications, organizational, and interpersonal skills; independent and interdependent work Project 3: VHDL Modeling of Wi-Fi Mac Layer for Transmitter and Receiver Module. (Jan 13- May 13, 2013)  Part of undergrad final project accomplished with a team of three. Took care of the project and team  Implemented IEEE 802.11 MAC receive controller with VHDL. Synthesis the modules in FPGA Xilinx and realize static timing analysis of transmitter and receiver modules  Learned valuable lesson about leadership skills and how to complete the project within deadline  Learned about the engineering topics, simultaneously tutoring the team, and presented at the end Project 4: Line follower robot using infrared sensors and 8051 microcontrollers. (Aug 12 – Dec 12, 2012)  This project is self-initiated and worked independently in my undergrad; interested in competing in robotics competitions between colleges; won first prize many times  Was able to customize and troubleshoot electrical designs  The objective of this project was to design an autonomous robot which was capable of following a path made of black line  L293D is used to drive motor and 8051 microcontrollers is used for programming and logic WORK EXPERIENCE Simulation lab coordinator (Graduate Assistant) School of Nursing, New Mexico State University, New Mexico, USA (Jan 2014 – December 2015)  Conducting simulation and pretending to be a patient in real life scenarios in a hospital setting (ICU/CCU)  Help professors by providing medical models and supply and allocating labs and classes for whole semester  Maintaining office records and ordering medical and supplies for office, labs, and class  Preparing documentations of events that happened during the semester, and reporting it to the school of nursing director and associate dean  Train new Graduate assistant hired for the next semester  Conducting tours for high school students at school of nursing  In charge of interviewing and hiring new graduate assistants VOLUNTEER EXPERIENCE  NM BEST Robotics Competition: Oct 10, 2015; robotics competition during which students participated in various activities; helping students with robotics, either in hardware or software, tutoring on coding in C and building the robots  Southwest Environmental Center: Oct 17, 2015; setup and teardown of the annual gala held by SWEC to fundraise for their animal rights projects  NMSU: Oct 17, 2015; Keep State Great; picked up trash in a corner of NMSU campus  Member of student IEEE; attending conferences and meetings in order to further my learning and help others understand their coursework more

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