RESUME
Shaik Naseeruddin
F-465, R.T.P.P., V.V.REDDYNAGAR COLONY,
KADAPA(DIST), Email: naseer_39@yahoo.in
ANDHRA PRADESH, I...
Year: July 2010 to October 2010 (4 months)
EDUCATIONAL QUALIFICATION
Degree: Bachelor of Technology (B.Tech), Madina Engin...
RESPONSIBILITY: Interface clearance for High Speed Rocket IO (i.e., SFP and SMA), QDRII SRAM,
and PCI-e IP Cores.
FPGA: Vi...
22 CONTROLLER DEVELOPMENT PLATFORM :
Introduction:
CDP is an integrated system which provide hardware platform to do HIL(h...
FPGA: Virtex 6
EDA TOOL: XILINX ISE
77 FIBER OPTIC MODEM (FOMODEM):
Introduction:
Fiber Optic Modem is a two channel board...
Personal Details:
Date of Birth: 04-06-1989.
Languages Known: Hindi, Telugu and English.
Nationality: Indian.
Marital Stat...
Personal Details:
Date of Birth: 04-06-1989.
Languages Known: Hindi, Telugu and English.
Nationality: Indian.
Marital Stat...
of 7

NASEERUDDIN RESUME

Published on: Mar 3, 2016
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Transcripts - NASEERUDDIN RESUME

  • 1. RESUME Shaik Naseeruddin F-465, R.T.P.P., V.V.REDDYNAGAR COLONY, KADAPA(DIST), Email: naseer_39@yahoo.in ANDHRA PRADESH, India –516312 Mobile: +91 9493440994/8897417615 OBJECTIVE To be an integral part of a respected and professional organization, where I can exploit myself in the field of FPGA, VLSI and ASIC and to keep myself updated with the cutting edge technologies. SUMMARY OF QUALIFICATIONS  Good understanding of the ASIC and FPGA design flow  Experience in writing RTL models in Verilog HDL and test benches.  HDL Code Generation using Simulink and System Generator.  Designed Different interfaces likes High speed RIO’s such as SFP, Memory Interfaces like QDRII SRAM,DDR2 SDRAM, Storage interfaces like SPI Flash, Parallel Flash and EEPROM, Communication interfaces like PCI-e, Backplane interfaces like VME64X and VPX and Interfaces like A/D and D/A converters.  Experience on MATLAB, System Generator, Simulink and Lab VIEW.  Experience in using industry standard EDA tools such as XILINX,LATTICE for the front-end design  Knowledge of AS9100 Rev.c Standards and Documentation. VLSI DOMAIN SKILLS HDLs: Verilog and Knowledge of VHDL. Software Skills: C. Mathematical Tools: MATLAB, Simulink and System Generator. HVL: Knowledge of System Verilog. EDA Tool: XILINX ISE, Modelsim, LATTICE DIAMOND. Domain: ASIC/FPGA Design Flow, Digital Design methodologies Knowledge: LINT, CDC, HDL Code Generation using MATLAB, Design and Development Process of Product, Type of FPGA’s, RTL Coding, and FSM based design, Simulation, Creating LABVIEW VI’s using DLL’s. PROFESSIONAL QUALIFICATION FPGA Design Engineer at Vrinda Technologies Year: November 2010 to April 2015 (4.6 Years). Maven Silicon Certified VLSI DESIGN course from Maven Silicon, Bangalore
  • 2. Year: July 2010 to October 2010 (4 months) EDUCATIONAL QUALIFICATION Degree: Bachelor of Technology (B.Tech), Madina Engineering College, Kadapa College: Madina Engineering College, Kadapa Discipline: Electronics and Communication Engineering Percentage: 68.8% First Class Year: May 2010 Degree: Intermediate Degree (12th ) College: Bhavana Junior College, Proddatur Discipline: Mathematics, Physics and Chemistry. Percentage: 74.9%. Year: April 2006 Degree: 10th Degree (S.S.C) School: D.A.V High School, R.T.P.P. Percentage: 83% Year: April 2004 ACHIEVEMENTS: • Got an award for the Best Performer of Year 2012-13 in Vrinda Technologies. EXPERIENCE November 2010- April 2015, Vrinda Technologies, FPGA Design Engineer Project Details 11 ELECTRONIC SUPPORT MEASURES: Electronic Support Measures (ESM) contains 3U VPX backplane based chassis which contain three 3 boards of interfaces like High speed Rocket IO’s (SFP and SMA), Memory Interfaces like QDRII SRAM, Processor(MPC8641D) and Communication interfaces like PCI-e. ROLE: Team Member TEAM SIZE: 4 members
  • 3. RESPONSIBILITY: Interface clearance for High Speed Rocket IO (i.e., SFP and SMA), QDRII SRAM, and PCI-e IP Cores. FPGA: Virtex-7 PROCESSOR: MPC8641D EDA TOOL: XILINX ISE 22 INTEGRATED FIELD SIGNAL SIMULATOR (as a Project Lead): Introduction: IFSS unit consists of a multiple slot standard VME chassis to accommodate the processor card and the IO modules. The processor card is interfaced to the LCD monitor, Keypad & mouse. It is interfaced to the other IO modules via backplane.IO Cards are Analog I/O’s, Digital I/O’s, Thermocouple I/O’s, RTD I/O’s and Pressure I/O’s.This application development API supports different platforms such as C, C++, FORTRAN, MATLAB and LAB VIEW. User friendly HMI software is provided for accessing and logging different I/O Channels. ROLE: Project Lead RESPONSIBILITY: RTL Design for all the IO CARDS, VME 64X slave and creating VI’s for data acquisition in LAB View, Managing Team Members, Scheduling the tasks and related Documentation. FPGA: SPARTAN 6 EDA TOOL: XILINX ISE 22 MULTISHOT DIGITAL CAMERA ON LINUX PLATFORM Introduction: The Multi-shot digital camera for Bore hole survey instrument is developed for the directional surveying of the bore holes, etc.This multishot instrument can take pictures of the magnetic compass at various depths and store the pictures in the USB device.The USB supports any make of any size. ROLE: Team Member TEAM SIZE: 7 members RESPONSIBILITY: RTL design for CMOS Sensor, MAG 3 Sensor, Optical Link and LM81 (Temperature Sensor). FPGA: LATTICE XP2 FPGA EDA TOOL: LATTICE DIAMOND
  • 4. 22 CONTROLLER DEVELOPMENT PLATFORM : Introduction: CDP is an integrated system which provide hardware platform to do HIL(hardware in loop) with the use of Graphical user friendly IDE (integrated development environment) running on real time operating system, for monitoring and processing of data from sensor both analog and digital signals. ROLE: Team Member TEAM SIZE: 8 members RESPONSIBILITY: HDL Code generation using MATLAB ,RTL design for IO CARDS (ADC’s and DAC’s), Slave Backplane controller and SPI Flash Interface FPGA: SPARTAN 6 FPGA EDA TOOL: XILINX ISE, MATLAB, Simulink and SYSTEM GENERATOR 22 BOREHOLE ONLINE SURVEY SYSTEM(BOSS) : Introduction: Borehole Online Survey System is surveyed to obtain the details about the path of the borehole. Borehole Online Survey System removes the path uncertainties in real time. Borehole Online Survey System mainly consists of PROBE, to get the pictures and the Magnetometer readings and the surface data acquisition unit at ground level, to display the captured information. ROLE: Team Member TEAM SIZE: 6 members RESPONSIBILITY: RTL design for Optical Link, CMOS sensor, MAG3 sensor, RS422, Processor Interface, DPRAM Interface and LM81. FPGA: SPARTAN 3(SDA) and Lattice XP2 (Probe) EDA TOOL: XILINX ISE AND LATTICE DIAMOND 22 BASELINE INTERFEROMETRY AND DIRECTION FINDING(BLIDF) : Introduction: The BLIDF processor unit receives phase from phase correlators and amplitude of video signals from EDLVA apart from the control signals and frequency data. It uses multiple ADC to serve the purpose. It has VPX backplane and operates in Industrial Grade temperature range. ROLE: Team Member TEAM SIZE: 5 members RESPONSIBILITY: RTL design for ADC’s and VPX Interface.
  • 5. FPGA: Virtex 6 EDA TOOL: XILINX ISE 77 FIBER OPTIC MODEM (FOMODEM): Introduction: Fiber Optic Modem is a two channel board which works in full duplex mode. Its main application is to receive the data from V.35 interface and process it and send on optical link to other end with different data rates from 56Kbps to 2048 Kbps. ROLE: Team Member TEAM SIZE: 7 members RESPONSIBILITY: RTL design for Optical Link Interface and Controller Communication Interface. FPGA: LATTICE ECP3 FPGA EDA TOOL: LATTICE DIAMOND PROCESSOR: POWER PC (MPC8280). VLSI COURSE Projects 77 SPI Master Core-Verification HVL: System Verilog EDA Tools: Modelsim– Verification Platform  Architected the verification environment using System Verilog.  Verified the RTL model using System Verilog.  Generated functional and code coverage for the RTL verification sign-off 77 Real Time Clock – RTL design HDL: Verilog HVL: System Verilog EDA Tools: Modelsim– Verification Platform and ISE  Implemented the Real Time Clock using Verilog HDL independently  Architected the verification environment using Verilog and System Verilog.  Verified the RTL model using Verilog and System Verilog.  Generated functional and code coverage for the RTL verification sign-off  Synthesized the design
  • 6. Personal Details: Date of Birth: 04-06-1989. Languages Known: Hindi, Telugu and English. Nationality: Indian. Marital Status: Single
  • 7. Personal Details: Date of Birth: 04-06-1989. Languages Known: Hindi, Telugu and English. Nationality: Indian. Marital Status: Single

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