Prevention of Data Loss in physical implementation of FIFOs and Data Synchronizers
Published on: Mar 4, 2016
Transcripts - Prevention of Data Loss in physical implementation of FIFOs and Data Synchronizers
Prevention of Data Loss in Physical Implementation of FIFOs and Data Path SynchronizersRamesh Rajagopalan (firstname.lastname@example.org), Cisco Systems Inc, San Jose, CAAjay Bhandari (email@example.com), Cisco Systems Inc, San Jose, CANamit Gupta (firstname.lastname@example.org), Atrenta Inc, San Jose, CA
Introduction: Asynchronous control and data bus domain crossingsNetwork switching ASICs have a multitude of IPs with different clock domains, at varying speeds that interface with a variety of buses and I/Os.Signals that cross clock boundaries create clock domain crossings (CDCs).Asynchronous crossings have no relationship between the sending and receiving clocks . This poster discusses only issues related to asynchronous clock domain crossings.Multi-flop synchronizers are used for a control signal’s asynchronous domain crossing to avoid meta-stability.In an asynchronous data bus transfer, the data is set up; then, a control signal that is synchronized with the destination domain enables data capture at the destination register. This relies on data to be stable when an enable is asserted.This requirement is addressed in logic design by extending the data pulse for a required number of cycles of destination clock so that the data is held when the enable is asserted.
Data loss issue and its prevention by logic design In an asynchronous data bus transfer, each valid transition on the source data should get captured in the destination domain to prevent data loss.To prevent data loss in a fast-to-slow clock domain data crossing: 1) Data must be held long enough to be registered by the destination flop. 2) Data should not change when the control (qualifier) signal that gates or enables the data crossing is active.Logic design ensures that 1) the data is held long enough by extending the data pulse for the time it takes to latch the data at the destination. 2) data is allowed to change only after receiving feedback from the destination domain after latching the current data.
Impact on physical design implementation of data path synchronizers During physical implementation of a data path synchronizer, the control signals from the source domain to the destination domain are timing-wise unconstrained in their path from the multi-flop synchronizers to the enable/mux-select or AND-based qualifiers. The unconstrained standard cell placement and detailed routing of the control path might result in a sub-optimal placement of the cells and scenic routing . As the technology node advanced, the RC interconnect values have increased by several folds especially for the lower routing layers. Higher net delay values could be seen for the control signal used as a synchronized enable at the qualifying gate of the domain crossing .
Unconstrained control and empty signal paths in Mux-select based andFIFO data synchronizers
Delay due to physical implementation impacting data transfer acrossClock Domains The impact of the large interconnect delay on the falling edge of the control signal is illustrated. The extended active enable signal would result in latching an unknown value of the data at thedestination domain. A similar issue occurs due to the delay in the rising edge of the control signalas well.
Need for a methodology to mitigate data loss due to physicalimplementation To mitigate the large physical net delay in the control signal, logic designers could introduce one more synchronizer register in the destination domain before sending the feedback to source domain to enable the data change to the next value. Such logic design-based solutions that introduce additional latencies would work for a given ratio of fast-to-slow clocks, with the control path delay due to physical implementation not exceeding one cycle of the destination clock. However, for designs: 1) that need to handle varying fast to slow clock ratios (as high as 10:1) based on different operating modes or due to use of the power reduction mode in the design, or 2) that are intolerant to any additional latency, or 3) that use very high layout utilization and are subject to local routing congestion, it would be better to physically constrain the control signal paths to place and route them within the allowed delay
Physical design methodology to mitigate data loss due to physical delayin enabling the fast-to-slow data crossingsPhysical Design methodology to be followed:3)Identify the destination register and the enable that gates the data crossing The SpyGlass® CDC tool in a CrossingInfo.rpt lists the “mux-select synchronizers”,“enable synchronizers”, “AND gate-based synchronizers” and “FIFOs” (with read pointer and write pointer instances).2) Using this information create an “instance group” of cells in the control path. Make this instance group into a soft guide for placement purposes in the Cadence EDI tool3) During cell placement, set the soft guide effort level to high to increase the degree of closeness between placement of the control path logic listed under a given soft guide.4) For improved results, pre-place the enable gating logic and fix it prior to incremental placement to get the cells in the soft guide placed near the fixed logic. Also, set a higher net weight on nets that need to be shorter.5) Create a max delay constraint from the last synchronizer register to the pin where the control gates the data crossings.6) Report timing for the control signal path (as an unconstrained path) and the analyze the actual delays for potential data loss.
Mux select control path : Reduction in net length/delay with suggested physical design methodology Logic View of Mux select control pathPhysical view - 1.5 mm long Mux select control Net length reduced to 130microns afterpath (Before using the suggested physical design using suggested physical methodologymethodology)
FIFO empty signal logic :Reduction in net length/delay by applying suggested physical design methodology Logical view – FIFO empty logicPhysical view - 430 microns long FIFO Net length reduced to 120 microns afterempty signal path (Before using the using suggested physical methodologysuggested physical design methodology)
Conclusion, Limitations and Future Work CONCLUSION: Prevention of data loss in a fast-to-slow clock domain data crossing needs to be addressed at both the logical and physical levels. The critical aspect is the implementation of a control path in a data synchronizer within the delay limit . Physical design techniques such as creating a soft guide for placement of control path logic proved to be very useful in bringing some guidance on the otherwise unconstrained control path. LIMITATIONS No single frame work or tool to infer destination domain registers and qualifier gates of CDC logic and create physical placement groups. FUTURE WORK Automation of the generation of the placement constraints is slated to be done in near future.